In digital receivers, it is important to obtain symbol synchronization by accurately sampling the received signal. A common technique to achieve accurate symbol sampling employs a timing error detector for controlling a numerically controlled oscillator in order to sample the received signal at the proper sampling times.
A typical example of a digital receiver incorporating a timing error detector is depicted in FIG. 1 as a digital receiver 10. The I and Q components of a demodulated digital signal are supplied to a resampler 12 of the digital receiver 10. The resampler 12 samples the demodulated I and Q components at twice the symbol rate. Thus, the resampler 12 provides two over-sampled sequences of T/2 sampled multibit symbol values (T=symbol period). The sampled signals are passed through a Root Raised Cosine (RRC) matched filter 14 to the input of a timing error detector 16. Also, a downsampler 18 downsamples the output of the Root Raised Cosine matched filter 14 by a factor of two in order to provide on an output 20 the multibit symbol values at the symbol rate.
The timing error detector 16 develops a timing error signal that is fed back through a loop filter 22 to adjust a numerically controlled oscillator 24 so as to provide a sampling control signal that accurately controls the resampler 12.
The so-called Gardner timing error detector is a known circuit that can be used for the timing error detector 16 of FIG. 1. A Gardner timing error detector 30 is shown in FIG. 2. The timing error detector 30 comprises two T/2 delay elements 32 and 34, a summer 36, and a multiplier 38. The timing error detector 30 receives multibit input samples at twice the symbol rate, and generates an output timing error signal for controlling the numerically controlled oscillator 24.
Accordingly, SN represents the current sample being input to the timing error detector 30, SC represents a sample which was input to the timing error detector 30 T/2 before the sample SN, and SP represents a sample which was input to the timing error detector 30 T/2 before the sample SC. The summer 36 subtracts the sample SP from the sample SN, and the multiplier 38 multiplies the result by the sample SC in order to produce a timing error e. Accordingly, the timing error detector 30 of FIG. 2 detects the timing error e according to the following equation:e=SC(SN−SP)  (1)
A waveform 40 representing the envelope of a demodulated received signal having binary valued symbols +1 and −1 is shown in FIG. 4. As can be seen from FIG. 4, the amplitude of the signal envelope of the waveform 40 at vertical lines 42 represents the received symbols. Proper sampling synchronization is achieved when the numerically controlled oscillator 24 of FIG. 1, in response to the filtered timing error signal e, produces a sampling signal for operating the resampler 12 to sample the waveform 40 at the sampling times represented by the circles along the horizontal axis of FIG. 4. This timing produces samples in exact time coincidence with the first two symbols and with one zero value sample in between these symbols.
In the case of proper sample timing as shown in FIG. 4, SC=0 so that the timing error e is zero and so that no adjustment is made to the numerically controlled oscillator 24. However, if the sampling signal lags the desired sampling signal, such as indicated by the squares in FIG. 4, the timing error e will be approximately e=−0.1(0.9−(−0.9))=−0.18 according to equation (1), where SC=−0.1, SN=0.9, and SP=−0.9 in this example. This timing error e is filtered by the loop filter 22 and is applied to the numerically controlled oscillator 24 so as to provide an adjustment to the resampler 12 tending to reduce the timing error e by causing sampling to occur slightly earlier in time.
Accordingly, if the sampling signal produced in response to the numerically controlled oscillator 24 is adjusted to cause sampling to occur in a leading relation to the desired sampling as represented by the triangles in FIG. 4, the timing error e will be approximately e=0.1(0.9−(−0.9))=0.18 according to equation (1), where SC=0.1, SN=0.9, and SP=−0.9 in this example. The result is that the timing error detector 30 operates the numerically controlled oscillator 24 to cause sampling to occur at or near the desired sampling points shown by the circles in FIG. 4.
The modified Gardner timing error detector is another known circuit that can be used for the timing error detector 16 of FIG. 1. FIG. 3 illustrates a modified Gardner timing error detector 50, which operates essentially in the same manner as the timing error detector 30 of FIG. 2. The timing error detector 50 reduces the effects of noise by using only the sign of SN and SP. The timing error detector 50 comprises two T/2 delay elements 52 and 54, a summer 56, a multiplier 58, and two sign operators 60 and 62. The timing error detector 50 also receives multibit input samples at twice the symbol rate, and generates an output timing error e for controlling the numerically controlled oscillator 24.
Accordingly, SN represents the current sample being input to the timing error detector 50, SC represents a sample which was input to the timing error detector 50 T/2 before the sample SN, and SP represents a sample which was input to the timing error detector 50 T/2 before the sample SC. The summer 56 subtracts a binary value having the sign of the sample SP from a binary value having the sign of the sample SN, and the multiplier 58 multiplies the result by the sample SC to produce the timing error e. Accordingly, the timing error detector 50 of FIG. 3 detects the timing error e according to the following equation:e=SC[sgn(SN)−sgn(SP)]  (2)
The timing error detectors 30 and 50 were designed for use in digital systems using binary valued symbols. Thus, although the timing error detectors 30 and 50 work relatively well with binary valued symbols, they do not work as well with symbols having more than two levels, such as those used in 8-VSB systems or in 16, 64, or 256 QAM systems.
The present invention provides an improved timing error detector for use when data having more than two levels, such as 8-VSB (8 level PAM) symbols or multi-level QAM symbols, are received. Thus, a Gardner-type timing error detector according to an embodiment of the present invention provides improved performance when used in systems employing multilevel symbol constellations. Such systems have more than two symbol levels and include, for example, pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM) systems. The improved performance obtained by the present invention contemplates faster convergence of the receiver with less noise.